U.S. Pat. No. 5,926,798 (Patent Document 1) discloses a flip-chip mount technology using a controlled collapse chip connection (C4) technology. This technology is a method for mounting a semiconductor chip (IC chip) on a printed wiring board. A semiconductor chip to be mounted has an array of a large number of solder bumps.
FIG. 14 is an enlarged cross-sectional view of the vicinity of a solder bump of a semiconductor package in which a semiconductor chip is mounted on a coreless substrate having no core substrate by the C4 technology. As shown in the drawing, the coreless substrate 1 includes a dielectric layer 2, a land 3, a via 4, and a connecting pad 5. The land 3 is shaped like a column (a thin disc) and is completely embedded in the dielectric layer 2. The connecting pad 5 is also a kind of land, shaped like a column (a thin disc), and is embedded in the dielectric layer 2, but the main surface 6 thereof is exposed at the main surface 7 of the dielectric layer 2. The via 4 is shaped like a truncated cone or a column, which is formed between the land 3 and the connecting pad 5 to electrically connect the land 3 and the connecting pad 5.
On the other hand, a semiconductor package 10 includes solder bumps 9 that constitute a bump array. A cushioning film 13 is formed on the bottom of a semiconductor chip 8 to absorb an impact applied on the solder bumps 9. Under bump metal (UBM) 11 is plated under the solder bumps 9 (between the solder bumps 9 and the bottom of the semiconductor chip 8).
The solder bumps 9 are mounted on the connecting pad 5, and solder 12, which is attached in advance, is melted to solder the solder bumps 9 to the connecting pad 5. Thus, the semiconductor chip 8 is mounted on the coreless substrate 1.
Here, the diameter φ1 of the connecting pad 5 is about 95 μm, and the diameter φ2 of the under bump metal 11 is about 75 μm, so that the diameter φ1 of the connecting pad 5 is larger than the diameter φ2 of the under bump metal 11. Therefore, if mechanical stress is applied in a direction in which the semiconductor chip 8 is separated from the coreless substrate 1, the stress concentrates onto the small-diameter under bump metal 11, from which rupture is prone to occur.
If the diameter φ1 of the connecting pad 5 can be made equal to the diameter φ2 of the under bump metal 11, mechanical stress may disperse evenly to both of the connecting pad 5 and the under bump metal 11, which may reduce rupture. However, those diameters cannot be made equal because of the following reasons.
The under bump metal 11 should be formed at a pitch of about 150 μm. However, if the diameter φ2 of the under bump metal 11 is increased, the distance from the adjacent under bump metals 11 decreases. This makes it difficult, in forming the under bump metals 11 by plate patterning, to remove unnecessary plate in the area other than the under bump metals 11, which reduces yields. On the other hand, it is also difficult to reduce the diameter φ1 of the connecting pad 5. This is because the limit of the diameter φ1 of the connecting pad 5 is 95 μm in consideration of the diameter of the via 4 and manufacturing tolerances of the position thereof.
Japanese Unexamined Patent Application Publication No. 2003-37135 (Patent Document 2) discloses a technology for a semiconductor device in which a semiconductor chip is mounted on a wiring board with bumps to ensure a predetermined height from the wiring board to the semiconductor chip (refer to Paragraph 0021 of Patent Document 2). The semiconductor chip is transported onto the wiring board and is bonded by aligning external terminals of the semiconductor chip and protruding conductors on the wiring board and performing thermocompression bonding. Solder balls are provided on the individual external terminals, with under bump metal therebetween, so that the height from the insulating substrate to the semiconductor chip after the solder balls are melted and bonded by thermocompression bonding can be increased by the height of the protruding conductors (refer to Paragraph 0055 of Patent Document 2). However, since the protruding conductors protrude from the wiring board, it is difficult to make the diameter of the joint surface between the external terminals of the semiconductor chip and the protruding conductors on the wiring board constant because of variations in the amount of the solder balls due to variations in manufacture, the mounting inclination of the semiconductor chip, and variations in mounting weight for the semiconductor chip.
Japanese Unexamined Patent Application Publication No. 10-242649 (Patent Document 3) discloses a multilayer printed wiring board having solder bumps (refer to FIGS. 19 and 20 of the gazette). This multilayer printed wiring board is provided with an electroless copper plating film and an electrolytic copper plating film, on which solder bumps are formed. This wiring board also has a solder resist thereon. However, portions where the copper plating films and the solder resist are stacked are protruded, and portions where no copper plating film is present and only the solder resist is present are recessed, so that the surface of the multilayer printed wiring board do not become flat. Therefore, underfill resin cannot be poured at a constant speed between the multilayer printed wiring board and the semiconductor chip mounted thereon.
Background information may also be found in [Patent Document 4] Japanese Unexamined Patent Application Publication No. 10-233417, and [Patent Document 5] Japanese Unexamined Patent Application Publication No. 2000-269271.